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OVERVIEW :: HDLC CONTROLLER :: OPENCORES Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. OVERVIEW :: WISHBONE BUS SPECIFICATIONS :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: CF FFT :: OPENCORES Each file is stand-alone and represents a specific configuration. The 2 parameters are: - Number of Points. - Component (Real/Imag) Precision. All designs are pipelined with a synchronous enable and reset. The configuration parameters are coded in the file names: cf_fft_4096_18.v. - 4K point FFT. OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: FLOATING POINT UNIT :: OPENCORESSEE MORE ON OPENCORES.ORG OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Viterbi HDL Code Generator. This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note inWISHBONE B4
Wishbone B4 Chapter 1. Introduction The WISHBONE1 System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a flexible design methodology for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating System-on-Chip integrationproblems.
HOME :: OPENCORESPROJECTSFORUMSABOUTHOWTO/FAQMEDIALICENSING The reference community for Free and Open Source gateware IP cores. Since 1999, OpenCores is the most prominent online community for the development of gateware IP (Intellectual Properties) Cores. It is the place where such cores are shared and promoted in the spirit of Free and Open Source collaboration. The OpenCores portal hosts the source OVERVIEW :: SYNCHRONOUS-DRAM CONTROLLER :: OPENCORES The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specifications. By default the core is configured to work with 512K x 2 Bank x 32-bit SDRAMs such asSamsung
OVERVIEW :: HDLC CONTROLLER :: OPENCORES Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. OVERVIEW :: WISHBONE BUS SPECIFICATIONS :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: CF FFT :: OPENCORES Each file is stand-alone and represents a specific configuration. The 2 parameters are: - Number of Points. - Component (Real/Imag) Precision. All designs are pipelined with a synchronous enable and reset. The configuration parameters are coded in the file names: cf_fft_4096_18.v. - 4K point FFT. OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: FLOATING POINT UNIT :: OPENCORESSEE MORE ON OPENCORES.ORG OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Viterbi HDL Code Generator. This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note inWISHBONE B4
Wishbone B4 Chapter 1. Introduction The WISHBONE1 System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a flexible design methodology for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating System-on-Chip integrationproblems.
OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORES The encoder accepts a parallel 8-bit raw input and generates a parallel 10-bit encoded value based on the data along with a running disparity value. The decoder does the reverse, providing a decoded 8-bit value from the 10-bit encoded input. These cores can be easily incorporated into serializer/deserializer (serdes) communicationsapplications.
OVERVIEW :: HARDWARE ASSISTED IEEE 1588 IP CORE :: OPENCORES Description. Hardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the Precision Time Protocol (IEEE 1588-2008) on 1000M/100M/10M Ethernet networks. PTP packets transmitting and receiving should be implemented by PTP SW protocol stack (PTPd) with existing MAC function; This IP Coreimplements
OVERVIEW :: T80 CPU :: OPENCORES Description. Configurable cpu core that supports Z80, 8080 and gameboy instruction sets. Z80 and 8080 compability have been proven by numerous implementations of old computer and arcade systems. It is used in the zxgate project, a zx81, zx spectrum, trs80 and Jupiter ACE clone project. And also in OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORES Description. Open Source Documented Verilog UART. Purpose. This module was created as a result of my own need for a UART (serial line I/O) component and frustration at the difficulty of integrating the existing available components in to my own project. OVERVIEW :: REED-SOLOMON DECODER/ENCODER :: OPENCORES Description. This core implements Reed-Solomon decoder for the 8-bit wide symbols. The core is designed to occupy fewer amounts of logic blocks, be fast and parametrizable. Main Features: 8-bit input and output data busses. Fully synchronous and pipelined design using OVERVIEW :: DDR3 SDRAM CONTROLLER :: OPENCORES Description. This is a controller core for DDR3 SDRAM. Default configuration supports one 64 bit UDIMM or SO-DIMM. Supports DIMM sizes of 1GB, 2GB, 4GB and 8GB. Works at the minimum DDR3 transfer rate of 600 MT/s. Heavily optimised for Xilinx Spartan 6 FPGA family. OVERVIEW :: MICRO FPGA BOARD :: OPENCORES Description. Micro FPGA board is a stand alone, low cost, do-it-yourself board. All components are possible to get from a local electronics shop (with possible exception of Virtex part). Board includes one Xilinx Virtex XCV100 chip. FPGA is loaded from PC via Xilinx XChecker cable and external power supply must be provided. OVERVIEW :: I2C SLAVE :: OPENCORES Description. i2cSlave is a minimalist I2C slave IP core that provides the basic framework for the implementation of custom I2C slave devices. The core provides a means to read and write up to 256 8-bit registers. These registers can be connected to the users custom logic, thus implementing a simple control and status interface. OVERVIEW :: SGMII :: OPENCORES License: GPL. Generic SGMII / 1000X module that can be connected to any transceiver technology. This core has been verified with 88E1111 Phy. - Autonegotiation. - Rx & Tx in 1000Mbps mode. - Slow bit rate ~ 10Mbps. I don't have adequate tools to verify at full speed. I I2C-MASTER CORE SPECIFICATION OpenCores I2C-Master core 06-03-01 www.opencores.org Rev 0.3 Preliminary 1 of 14 1 Introduction I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of HOME :: OPENCORESPROJECTSFORUMSABOUTHOWTO/FAQMEDIALICENSING The reference community for Free and Open Source gateware IP cores. Since 1999, OpenCores is the most prominent online community for the development of gateware IP (Intellectual Properties) Cores. It is the place where such cores are shared and promoted in the spirit of Free and Open Source collaboration. The OpenCores portal hosts the source OVERVIEW :: SYNCHRONOUS-DRAM CONTROLLER :: OPENCORES The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specifications. By default the core is configured to work with 512K x 2 Bank x 32-bit SDRAMs such asSamsung
OVERVIEW :: HDLC CONTROLLER :: OPENCORES Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. OVERVIEW :: WISHBONE BUS SPECIFICATIONS :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: CF FFT :: OPENCORES Each file is stand-alone and represents a specific configuration. The 2 parameters are: - Number of Points. - Component (Real/Imag) Precision. All designs are pipelined with a synchronous enable and reset. The configuration parameters are coded in the file names: cf_fft_4096_18.v. - 4K point FFT. OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: FLOATING POINT UNIT :: OPENCORESSEE MORE ON OPENCORES.ORG OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Viterbi HDL Code Generator. This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note inWISHBONE B4
Wishbone B4 Chapter 1. Introduction The WISHBONE1 System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a flexible design methodology for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating System-on-Chip integrationproblems.
HOME :: OPENCORESPROJECTSFORUMSABOUTHOWTO/FAQMEDIALICENSING The reference community for Free and Open Source gateware IP cores. Since 1999, OpenCores is the most prominent online community for the development of gateware IP (Intellectual Properties) Cores. It is the place where such cores are shared and promoted in the spirit of Free and Open Source collaboration. The OpenCores portal hosts the source OVERVIEW :: SYNCHRONOUS-DRAM CONTROLLER :: OPENCORES The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specifications. By default the core is configured to work with 512K x 2 Bank x 32-bit SDRAMs such asSamsung
OVERVIEW :: HDLC CONTROLLER :: OPENCORES Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. OVERVIEW :: WISHBONE BUS SPECIFICATIONS :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: CF FFT :: OPENCORES Each file is stand-alone and represents a specific configuration. The 2 parameters are: - Number of Points. - Component (Real/Imag) Precision. All designs are pipelined with a synchronous enable and reset. The configuration parameters are coded in the file names: cf_fft_4096_18.v. - 4K point FFT. OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: FLOATING POINT UNIT :: OPENCORESSEE MORE ON OPENCORES.ORG OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Viterbi HDL Code Generator. This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note inWISHBONE B4
Wishbone B4 Chapter 1. Introduction The WISHBONE1 System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a flexible design methodology for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating System-on-Chip integrationproblems.
OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORES The encoder accepts a parallel 8-bit raw input and generates a parallel 10-bit encoded value based on the data along with a running disparity value. The decoder does the reverse, providing a decoded 8-bit value from the 10-bit encoded input. These cores can be easily incorporated into serializer/deserializer (serdes) communicationsapplications.
OVERVIEW :: HARDWARE ASSISTED IEEE 1588 IP CORE :: OPENCORES Description. Hardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the Precision Time Protocol (IEEE 1588-2008) on 1000M/100M/10M Ethernet networks. PTP packets transmitting and receiving should be implemented by PTP SW protocol stack (PTPd) with existing MAC function; This IP Coreimplements
OVERVIEW :: T80 CPU :: OPENCORES Description. Configurable cpu core that supports Z80, 8080 and gameboy instruction sets. Z80 and 8080 compability have been proven by numerous implementations of old computer and arcade systems. It is used in the zxgate project, a zx81, zx spectrum, trs80 and Jupiter ACE clone project. And also in OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORES Description. Open Source Documented Verilog UART. Purpose. This module was created as a result of my own need for a UART (serial line I/O) component and frustration at the difficulty of integrating the existing available components in to my own project. OVERVIEW :: REED-SOLOMON DECODER/ENCODER :: OPENCORES Description. This core implements Reed-Solomon decoder for the 8-bit wide symbols. The core is designed to occupy fewer amounts of logic blocks, be fast and parametrizable. Main Features: 8-bit input and output data busses. Fully synchronous and pipelined design using OVERVIEW :: DDR3 SDRAM CONTROLLER :: OPENCORES Description. This is a controller core for DDR3 SDRAM. Default configuration supports one 64 bit UDIMM or SO-DIMM. Supports DIMM sizes of 1GB, 2GB, 4GB and 8GB. Works at the minimum DDR3 transfer rate of 600 MT/s. Heavily optimised for Xilinx Spartan 6 FPGA family. OVERVIEW :: MICRO FPGA BOARD :: OPENCORES Description. Micro FPGA board is a stand alone, low cost, do-it-yourself board. All components are possible to get from a local electronics shop (with possible exception of Virtex part). Board includes one Xilinx Virtex XCV100 chip. FPGA is loaded from PC via Xilinx XChecker cable and external power supply must be provided. OVERVIEW :: I2C SLAVE :: OPENCORES Description. i2cSlave is a minimalist I2C slave IP core that provides the basic framework for the implementation of custom I2C slave devices. The core provides a means to read and write up to 256 8-bit registers. These registers can be connected to the users custom logic, thus implementing a simple control and status interface. OVERVIEW :: SGMII :: OPENCORES License: GPL. Generic SGMII / 1000X module that can be connected to any transceiver technology. This core has been verified with 88E1111 Phy. - Autonegotiation. - Rx & Tx in 1000Mbps mode. - Slow bit rate ~ 10Mbps. I don't have adequate tools to verify at full speed. I I2C-MASTER CORE SPECIFICATION OpenCores I2C-Master core 06-03-01 www.opencores.org Rev 0.3 Preliminary 1 of 14 1 Introduction I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of OVERVIEW :: SYNCHRONOUS-DRAM CONTROLLER :: OPENCORES The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specifications. By default the core is configured to work with 512K x 2 Bank x 32-bit SDRAMs such asSamsung
OVERVIEW :: HDLC CONTROLLER :: OPENCORES Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. OVERVIEW :: CF FFT :: OPENCORES Each file is stand-alone and represents a specific configuration. The 2 parameters are: - Number of Points. - Component (Real/Imag) Precision. All designs are pipelined with a synchronous enable and reset. The configuration parameters are coded in the file names: cf_fft_4096_18.v. - 4K point FFT. OVERVIEW :: TERNARY (3-INPUT) ADDER :: OPENCORES Other project properties. This IP core provides resource efficient ternary adders, i.e., adders with three inputs performing s = x + y + z, for the Altera and Xilinx platforms. Resource efficient means that they need exactly the same resources on modern FPGAs as two-input adders, but are slightly slower. Note that the used method for theXilinx
OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Viterbi HDL Code Generator. This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in OVERVIEW :: PCI TARGET :: OPENCORESSEE MORE ON OPENCORES.ORG OVERVIEW :: UART16750 :: OPENCORES Status. - Test script creation done, should cover most functions. - Test log file available. The core was synthesized on a Altera Cyclone II, connected to x86. standard hardware and than tested with standard OS drivers from: - Linux 2.2/2.4/2.6. - Windows 2000/XP/Vista. - *BSD. I2C-MASTER CORE SPECIFICATION OpenCores I2C-Master core 06-03-01 www.opencores.org Rev 0.3 Preliminary 1 of 14 1 Introduction I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method ofOPENCORES
DS18B20 (temp sensor) using 1-wire by Cottty on Jun 28, 2017 Quote: Cottty Posts: 1 Joined: Apr 1, 2017 OVERVIEW :: SYNCHRONOUS-DRAM CONTROLLER :: OPENCORES The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specifications. By default the core is configured to work with 512K x 2 Bank x 32-bit SDRAMs such asSamsung
OVERVIEW :: HDLC CONTROLLER :: OPENCORES Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. OVERVIEW :: CF FFT :: OPENCORES Each file is stand-alone and represents a specific configuration. The 2 parameters are: - Number of Points. - Component (Real/Imag) Precision. All designs are pipelined with a synchronous enable and reset. The configuration parameters are coded in the file names: cf_fft_4096_18.v. - 4K point FFT. OVERVIEW :: TERNARY (3-INPUT) ADDER :: OPENCORES Other project properties. This IP core provides resource efficient ternary adders, i.e., adders with three inputs performing s = x + y + z, for the Altera and Xilinx platforms. Resource efficient means that they need exactly the same resources on modern FPGAs as two-input adders, but are slightly slower. Note that the used method for theXilinx
OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Viterbi HDL Code Generator. This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in OVERVIEW :: PCI TARGET :: OPENCORESSEE MORE ON OPENCORES.ORG OVERVIEW :: UART16750 :: OPENCORES Status. - Test script creation done, should cover most functions. - Test log file available. The core was synthesized on a Altera Cyclone II, connected to x86. standard hardware and than tested with standard OS drivers from: - Linux 2.2/2.4/2.6. - Windows 2000/XP/Vista. - *BSD. I2C-MASTER CORE SPECIFICATION OpenCores I2C-Master core 06-03-01 www.opencores.org Rev 0.3 Preliminary 1 of 14 1 Introduction I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method ofOPENCORES
DS18B20 (temp sensor) using 1-wire by Cottty on Jun 28, 2017 Quote: Cottty Posts: 1 Joined: Apr 1, 2017 OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORES Description. Open Source Documented Verilog UART. Purpose. This module was created as a result of my own need for a UART (serial line I/O) component and frustration at the difficulty of integrating the existing available components in to my own project. OVERVIEW :: HARDWARE ASSISTED IEEE 1588 IP CORE :: OPENCORES Description. Hardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the Precision Time Protocol (IEEE 1588-2008) on 1000M/100M/10M Ethernet networks. PTP packets transmitting and receiving should be implemented by PTP SW protocol stack (PTPd) with existing MAC function; This IP Coreimplements
OVERVIEW :: SPI CONTROLLER CORE :: OPENCORES Description. SPI (Serial Peripheral Interface) is serial, synchronous, full duplex communication protocol. It is widely used as a board-level interface between different devices such as microcontrollers, DACs, ADCs and others. This core is SPI/Microwire compliant master serial communication controller with additional functionality. OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORES The encoder accepts a parallel 8-bit raw input and generates a parallel 10-bit encoded value based on the data along with a running disparity value. The decoder does the reverse, providing a decoded 8-bit value from the 10-bit encoded input. These cores can be easily incorporated into serializer/deserializer (serdes) communicationsapplications.
OVERVIEW :: REED-SOLOMON DECODER/ENCODER :: OPENCORES Description. This core implements Reed-Solomon decoder for the 8-bit wide symbols. The core is designed to occupy fewer amounts of logic blocks, be fast and parametrizable. Main Features: 8-bit input and output data busses. Fully synchronous and pipelined design using OVERVIEW :: SGMII :: OPENCORES License: GPL. Generic SGMII / 1000X module that can be connected to any transceiver technology. This core has been verified with 88E1111 Phy. - Autonegotiation. - Rx & Tx in 1000Mbps mode. - Slow bit rate ~ 10Mbps. I don't have adequate tools to verify at full speed. I OVERVIEW :: PCI TARGET :: OPENCORES The PCI32tLite IP core provides the funtionality of a PCI TARGET. The core has been designed to permit interface between a PCI Master and simple WHISBONE Slaves, and fitting into smallest FPGA (about 200 LC's in ALTERA CYCLONE II FPGA). Whisbone databus size and endianess configurable: "BIG"/"LITTLE",32/16/8 bits. OVERVIEW :: JTAG MASTER :: OPENCORES Description. This is a JTAG Master written in VHDL. It's simulated and tested with XC9500 and the jtag slave from opencores (http://opencores.orgproject,jtag) OVERVIEW :: SMARTCARD INTERFACE (ISO7816-3) :: OPENCORES Description. This project's aim is to provide the smart-card side of an ISO 7816-3 interface. Features - Detects reset and sends ATR(Answer to Reset).
OPENCORES
100 rem this program plays 3d tic-tac-toe: 110 dim s(76),r(304),w(20),t(3,14),m(64),l(4) 120 for i=89 to 304: read r(i): next i: 125 for i=1 to 20: read w(i): next i OVERVIEW :: SYNCHRONOUS-DRAM CONTROLLER :: OPENCORES Description. The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Features - direct traceback option. - self test automation - support any popular convolution code. - throughput and area of decoder arescalable.
OVERVIEW :: HDLC CONTROLLER :: OPENCORES Vendor: Device: Size: Frequency Board Tested: Functional Test: Notes: Altera: EP20K100BC356-3: 108 LCs: 91.48MHz--No optimization was peroformed, using Quartus II OVERVIEW :: CF FFT :: OPENCORES Description. Cores are generated from Confluence; a modern logic design language.Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C. See Confluent for more info. The Fast Fourier Transform converts time or spacial information into the frequency domain and is one of the most popular DSP algorithms. OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: PCI TARGET :: OPENCORESSEE MORE ON OPENCORES.ORG OVERVIEW :: UART16750 :: OPENCORES Description. Implements a 16550/16750 UART core. Features - Full synchronous design - Pin compatible to 16550/16750 - Register compatible to 16550/16750 OVERVIEW :: JTAG MASTER :: OPENCORES Description. This is a JTAG Master written in VHDL. It's simulated and tested with XC9500 and the jtag slave from opencores (http://opencores.orgproject,jtag) I2C-MASTER CORE SPECIFICATION OpenCores I2C-Master core 06-03-01 www.opencores.org Rev 0.3 Preliminary 1 of 14 1 Introduction I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method ofOPENCORES
ARINC 429 Core by sudhagutta on Feb 8, 2005 Quote: sudhagutta Posts: 3Joined: Feb 9, 2005
OVERVIEW :: SYNCHRONOUS-DRAM CONTROLLER :: OPENCORES Description. The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Features - direct traceback option. - self test automation - support any popular convolution code. - throughput and area of decoder arescalable.
OVERVIEW :: HDLC CONTROLLER :: OPENCORES Vendor: Device: Size: Frequency Board Tested: Functional Test: Notes: Altera: EP20K100BC356-3: 108 LCs: 91.48MHz--No optimization was peroformed, using Quartus II OVERVIEW :: CF FFT :: OPENCORES Description. Cores are generated from Confluence; a modern logic design language.Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C. See Confluent for more info. The Fast Fourier Transform converts time or spacial information into the frequency domain and is one of the most popular DSP algorithms. OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: PCI TARGET :: OPENCORESSEE MORE ON OPENCORES.ORG OVERVIEW :: UART16750 :: OPENCORES Description. Implements a 16550/16750 UART core. Features - Full synchronous design - Pin compatible to 16550/16750 - Register compatible to 16550/16750 OVERVIEW :: JTAG MASTER :: OPENCORES Description. This is a JTAG Master written in VHDL. It's simulated and tested with XC9500 and the jtag slave from opencores (http://opencores.orgproject,jtag) I2C-MASTER CORE SPECIFICATION OpenCores I2C-Master core 06-03-01 www.opencores.org Rev 0.3 Preliminary 1 of 14 1 Introduction I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method ofOPENCORES
ARINC 429 Core by sudhagutta on Feb 8, 2005 Quote: sudhagutta Posts: 3Joined: Feb 9, 2005
OVERVIEW :: PCI TARGET :: OPENCORES Description. The PCI32tLite IP core provides the funtionality of a PCI TARGET. The core has been designed to permit interface between a PCI Master and simple WHISBONE Slaves, and fitting into smallest FPGA (about 200 LC's in ALTERA CYCLONE II FPGA). OVERVIEW :: MICRO FPGA BOARD :: OPENCORES Description. Micro FPGA board is a stand alone, low cost, do-it-yourself board. All components are possible to get from a local electronics shop (with possible exception of Virtex part). OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORES Description. Open Source Documented Verilog UART. Purpose. This module was created as a result of my own need for a UART (serial line I/O) component and frustration at the difficulty of integrating the existing available components in to my own project. OVERVIEW :: SPI CONTROLLER CORE :: OPENCORES Description. SPI (Serial Peripheral Interface) is serial, synchronous, full duplex communication protocol. It is widely used as a board-level interface between different devices such as OVERVIEW :: UNSIGNED SERIAL DIVIDER :: OPENCORES Description. The serial_divide_uu is a Verilog coded module that performs binary division. It is fully parameterized, and works in aserial fashion.
OVERVIEW :: REED-SOLOMON DECODER/ENCODER :: OPENCORES Description. This core implements Reed-Solomon decoder for the 8-bit wide symbols. The core is designed to occupy fewer amounts of logic blocks, be fast and parametrizable. OVERVIEW :: SGMII :: OPENCORES Description. Generic SGMII / 1000X module that can be connected to any transceiver technology. This core has been verified with 88E1111 Phy -Autonegotiation
OVERVIEW :: JTAG MASTER :: OPENCORES Description. This is a JTAG Master written in VHDL. It's simulated and tested with XC9500 and the jtag slave from opencores (http://opencores.orgproject,jtag) OVERVIEW :: RISC16F84 :: OPENCORES Description. The risc16f84 project is intended to provide a small, easy to use microcontroller in Verilog. The original code was VHDL, but I have done a wonderful translation of it into good clean Verilogcode.
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100 rem this program plays 3d tic-tac-toe: 110 dim s(76),r(304),w(20),t(3,14),m(64),l(4) 120 for i=89 to 304: read r(i): next i: 125 for i=1 to 20: read w(i): next i HOME :: OPENCORESPROJECTSFORUMSABOUTHOWTO/FAQMEDIALICENSING The reference community for Free and Open Source gateware IP cores. Since 1999, OpenCores is the most prominent online community for the development of gateware IP (Intellectual Properties) Cores. It is the place where such cores are shared and promoted in the spirit of Free and Open Source collaboration. The OpenCores portal hosts the source OVERVIEW :: SYNCHRONOUS-DRAM CONTROLLER :: OPENCORES The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specifications. By default the core is configured to work with 512K x 2 Bank x 32-bit SDRAMs such asSamsung
OVERVIEW :: HDLC CONTROLLER :: OPENCORES Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Viterbi HDL Code Generator. This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: MICRO FPGA BOARD :: OPENCORES Description. Micro FPGA board is a stand alone, low cost, do-it-yourself board. All components are possible to get from a local electronics shop (with possible exception of Virtex part). Board includes one Xilinx Virtex XCV100 chip. FPGA is loaded from PC via Xilinx XChecker cable and external power supply must be provided. OVERVIEW :: WISHBONE BUS SPECIFICATIONS :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: HARDWARE ASSISTED IEEE 1588 IP CORE :: OPENCORESSEE MOREON OPENCORES.ORG
SPI MASTER CORE SPECIFICATION OpenCores SPI Master Core Specification 3/15/2004 www.opencores.org Rev 0.5 i Revision History Rev. Date Author Description 0.1 June 13, 2002 Simon Srot First DraftWISHBONE B4
Wishbone B4 Chapter 1. Introduction The WISHBONE1 System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a flexible design methodology for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating System-on-Chip integrationproblems.
HOME :: OPENCORESPROJECTSFORUMSABOUTHOWTO/FAQMEDIALICENSING The reference community for Free and Open Source gateware IP cores. Since 1999, OpenCores is the most prominent online community for the development of gateware IP (Intellectual Properties) Cores. It is the place where such cores are shared and promoted in the spirit of Free and Open Source collaboration. The OpenCores portal hosts the source OVERVIEW :: SYNCHRONOUS-DRAM CONTROLLER :: OPENCORES The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specifications. By default the core is configured to work with 512K x 2 Bank x 32-bit SDRAMs such asSamsung
OVERVIEW :: HDLC CONTROLLER :: OPENCORES Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Viterbi HDL Code Generator. This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: MICRO FPGA BOARD :: OPENCORES Description. Micro FPGA board is a stand alone, low cost, do-it-yourself board. All components are possible to get from a local electronics shop (with possible exception of Virtex part). Board includes one Xilinx Virtex XCV100 chip. FPGA is loaded from PC via Xilinx XChecker cable and external power supply must be provided. OVERVIEW :: WISHBONE BUS SPECIFICATIONS :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: HARDWARE ASSISTED IEEE 1588 IP CORE :: OPENCORESSEE MOREON OPENCORES.ORG
SPI MASTER CORE SPECIFICATION OpenCores SPI Master Core Specification 3/15/2004 www.opencores.org Rev 0.5 i Revision History Rev. Date Author Description 0.1 June 13, 2002 Simon Srot First DraftWISHBONE B4
Wishbone B4 Chapter 1. Introduction The WISHBONE1 System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a flexible design methodology for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating System-on-Chip integrationproblems.
OVERVIEW :: MICRO FPGA BOARD :: OPENCORES Description. Micro FPGA board is a stand alone, low cost, do-it-yourself board. All components are possible to get from a local electronics shop (with possible exception of Virtex part). Board includes one Xilinx Virtex XCV100 chip. FPGA is loaded from PC via Xilinx XChecker cable and external power supply must be provided. OPENCORES: EDA TOOLS :: OPENCORES Icarus Verilog Simulator. Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the "vvp" command. OVERVIEW :: APB TO SPI :: OPENCORES Description. APB SPI design is meant to be interfaced with slow-speed peripherals. The initial design will contain APB slave on one side, which will initiate the transactions which can read data from and write data to SPI peripheral. Since SPI is a serial interface, in case of a write, the design will ensure that data obtained through the APB OVERVIEW :: FLOATING POINT UNIT :: OPENCORES Description. This is a single precision floating point unit. It is fully IEEE 754 compliant. It can currently perform Add/Sub, Mul and Divide operations, as well as integer to floating point and floating point to integer conversions. It supports four rounding modes: Round to Nearest Even, Round to Zero, Round to +INF and Round to -INF. OVERVIEW :: HARDWARE ASSISTED IEEE 1588 IP CORE :: OPENCORES Description. Hardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the Precision Time Protocol (IEEE 1588-2008) on 1000M/100M/10M Ethernet networks. PTP packets transmitting and receiving should be implemented by PTP SW protocol stack (PTPd) with existing MAC function; This IP Coreimplements
OVERVIEW :: VIDEO STREAM SCALER :: OPENCORES Description. The Video Stream Scaler scales streaming video up or down in resolution. Bilinear and nearest neighbor resize. modes are supported. This core provides run-time adjustment of input and output resolution, scaling factors, and scale. type. Compile time OVERVIEW :: SGMII :: OPENCORES License: GPL. Generic SGMII / 1000X module that can be connected to any transceiver technology. This core has been verified with 88E1111 Phy. - Autonegotiation. - Rx & Tx in 1000Mbps mode. - Slow bit rate ~ 10Mbps. I don't have adequate tools to verify at full speed. I OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORES A UART is a useful component for controlling asynchronous (without a separate clock line) serial buses. It can be used via a level converter to talk to the RS232 serial port of a computer. This is not, however, the only application. It can also be used in a circuit to communicate with peripherals, or over other types of cables (such atRS485
OVERVIEW :: SD CARD CONTROLLER :: OPENCORES The "sd card controller" is a Secure Digital Card Host Controller, which main focus is to provide fast and simple interface to SD/SDHC cards. One of the main goal with this project is that the controller should be usable as a system disk contain a file system. Therefore the core has been developed with features a system with operative systemOPENCORES
100 rem this program plays 3d tic-tac-toe: 110 dim s(76),r(304),w(20),t(3,14),m(64),l(4) 120 for i=89 to 304: read r(i): next i: 125 for i=1 to 20: read w(i): next i HOME :: OPENCORESPROJECTSFORUMSABOUTHOWTO/FAQMEDIALICENSING The reference community for Free and Open Source gateware IP cores. Since 1999, OpenCores is the most prominent online community for the development of gateware IP (Intellectual Properties) Cores. It is the place where such cores are shared and promoted in the spirit of Free and Open Source collaboration. The OpenCores portal hosts the source OVERVIEW :: SYNCHRONOUS-DRAM CONTROLLER :: OPENCORES The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specifications. By default the core is configured to work with 512K x 2 Bank x 32-bit SDRAMs such asSamsung
PROJECTS :: OPENCORES Projects :: OpenCores. Written in: Any language VHDL Verilog & VHDL Verilog SystemC Bluespec C/C++ Other. Stage: Any stage Planning Mature Alpha Beta Stable. License: Any license GPL LGPL BSD CERN-OHL-S CERN-OHL-L CERN-OHL2-P Others. Wishbone version: OVERVIEW :: HDLC CONTROLLER :: OPENCORES Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: CF FFT :: OPENCORES Each file is stand-alone and represents a specific configuration. The 2 parameters are: - Number of Points. - Component (Real/Imag) Precision. All designs are pipelined with a synchronous enable and reset. The configuration parameters are coded in the file names: cf_fft_4096_18.v. - 4K point FFT. OVERVIEW :: FLOATING POINT UNIT :: OPENCORESSEE MORE ON OPENCORES.ORG OVERVIEW :: JTAG MASTER :: OPENCORES Description. This is a JTAG Master written in VHDL. It's simulated and tested with XC9500 and the jtag slave from opencores (http://opencores.orgproject,jtag) OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Viterbi HDL Code Generator. This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in OVERVIEW :: A VHDL 16550 UART CORE :: OPENCORES 18 Aug 2007. add stopB to sensitivity list in TX module (works the same, but removes warning) 12 Oct 2007. fixed the bug reports (dated 10/11 Oct 2007) THRE Interrupt will now be generated when trans FIFO is empty and interrupt enable bit changes from disabled to enabled. (note on THRE operation added par 3.3) The Receiver Line StatusInterrupt
HOME :: OPENCORESPROJECTSFORUMSABOUTHOWTO/FAQMEDIALICENSING The reference community for Free and Open Source gateware IP cores. Since 1999, OpenCores is the most prominent online community for the development of gateware IP (Intellectual Properties) Cores. It is the place where such cores are shared and promoted in the spirit of Free and Open Source collaboration. The OpenCores portal hosts the source OVERVIEW :: SYNCHRONOUS-DRAM CONTROLLER :: OPENCORES The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specifications. By default the core is configured to work with 512K x 2 Bank x 32-bit SDRAMs such asSamsung
PROJECTS :: OPENCORES Projects :: OpenCores. Written in: Any language VHDL Verilog & VHDL Verilog SystemC Bluespec C/C++ Other. Stage: Any stage Planning Mature Alpha Beta Stable. License: Any license GPL LGPL BSD CERN-OHL-S CERN-OHL-L CERN-OHL2-P Others. Wishbone version: OVERVIEW :: HDLC CONTROLLER :: OPENCORES Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: CF FFT :: OPENCORES Each file is stand-alone and represents a specific configuration. The 2 parameters are: - Number of Points. - Component (Real/Imag) Precision. All designs are pipelined with a synchronous enable and reset. The configuration parameters are coded in the file names: cf_fft_4096_18.v. - 4K point FFT. OVERVIEW :: FLOATING POINT UNIT :: OPENCORESSEE MORE ON OPENCORES.ORG OVERVIEW :: JTAG MASTER :: OPENCORES Description. This is a JTAG Master written in VHDL. It's simulated and tested with XC9500 and the jtag slave from opencores (http://opencores.orgproject,jtag) OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Viterbi HDL Code Generator. This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in OVERVIEW :: A VHDL 16550 UART CORE :: OPENCORES 18 Aug 2007. add stopB to sensitivity list in TX module (works the same, but removes warning) 12 Oct 2007. fixed the bug reports (dated 10/11 Oct 2007) THRE Interrupt will now be generated when trans FIFO is empty and interrupt enable bit changes from disabled to enabled. (note on THRE operation added par 3.3) The Receiver Line StatusInterrupt
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The reference community for Free and Open Source gateware IP cores. Since 1999, OpenCores is the most prominent online community for the development of gateware IP (Intellectual Properties) Cores. It is the place where such cores are shared and promoted in the spirit of Free and Open Source collaboration. The OpenCores portal hosts the source PROJECTS :: OPENCORES Any language VHDL Verilog & VHDL Verilog SystemC Bluespec C/C++ Other. Stage: Any stage Planning Mature Alpha Beta Stable. License: Any license GPL LGPL BSD CERN-OHL-S CERN-OHL-L CERN-OHL2-P Others. Wishbone version: Any version B.3 B.4. ASIC proven Design done FPGA proven Specification done OpenCores Certified.OPENCORES
Tools . © copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. PROJECTS :: OPENCORES Projects :: OpenCores. Written in: Any language VHDL Verilog & VHDL Verilog SystemC Bluespec C/C++ Other. Stage: Any stage Planning Mature Alpha Beta Stable. License: Any license GPL LGPL BSD CERN-OHL-S CERN-OHL-L CERN-OHL2-P Others. Wishbone version: OVERVIEW :: SHA256 HASH CORE :: OPENCORES The SHA256 hash is a block transformation algorithm based on LFSR message expansion. The algorithm has 2 parts: the Message Schedule and the Hash Core. The message schedule can be implemented as a compact 16-word circular buffer, that is cycled for the 64 clock cycles. Here is a simplified diagram of our implementation of the message schedule OVERVIEW :: OPEN8 URISC :: OPENCORES 8-bit RISC processor core based on the Vautomation uRISC. This is a "clean" reimplementation of the Vautomation uRISC processor core (aka the "V8", also named the Arclite core) based on ISA documentation only. It implements the full v8 architecture with a few additions, most of which are optional: * Thirty-six basic instructions (and fournew
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https://opencores.org/ocsvn/complex-gaussian-pseudo-random-number-generator/complex-gaussian-pseudo-random-number-generator/trunkOPENCORES
Compare Revisions. This comparison shows the changes necessary to convert path /async_sdm_noc from Rev 38 to Rev 39 ↔ Reversecomparison
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20/08/2008 Initial version. 30/09/2010 Use template style packet definition. 16/10/2010 Support SDM. OVERVIEW :: I2C CONTROLLER WISHBONE WRAPPER :: OPENCORES Description. Short: virtually convert an I2C slave into a WISHBONE slave This is a wrapper for the I2C controller core by Richard Herveille (http://opencoresUsername:
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Sigasi launches Open Source Program by Brosens,Bart on 05-14-2021
# Use Sigasi Studio with your Open Source projects **Sigasi supports the open source community. We already are contributing to the opensource software...
⭐⭐⭐⭐⭐ Sensor networks for agriculture based on #FPGA by Asanza, Victor on 03-20-2021 ✅ Objectives: Acquire signals from humidity sensors located on a porous surface, sunlight, air temperature and humidity. Compare the performance of at... Epileptic Seizure Prediction with #MachineLearning based on #FPGA by Asanza, Victor on 02-04-2021 ✅ Goals: Implementar un Sistema Embebido basado en #FPGA que lea datos preprocesados (.csv o .mat) almacenados en memoria Double Data Rate 3 Synchronous... REGISTERED OPENCORES USERS 336243 OpenCores statistics LAST UPDATED PROJECTS * FT816Float - Floating point accelerator * The NEORV32 Processor (RISC-V) * Generic Booth Multiplier * Special Functions Units (SFU)* MIX-fpga
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* Configurable AES-GCM 128-192-256 bits MOST POPULAR PROJECTS * I2C controller core * SPI Verilog Master & Slave modules * SPI Master/Slave Interface* I2C Slave
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* I2C master/slave Core * 10_100_1000 Mbps tri-mode ethernet MAC * CAN Protocol Controller copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.Details
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