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U7KARSH.COM
About Me. Currently working at Nvidia as a Sr. Architect, CPU. An avid skydiving enthusiast! Past experience includes Marvell Semiconductors (ThunderX4 architecture team), Cadence Design Systems (Verification IP @ HDMI, I2C, MHL, USB type-C) M.S. thesis in Computer Engineering from NCSU under the guidance of Prof. Eric Rotenberg.U7KARSH.COM
About Me. Currently working at Nvidia as a Sr. Architect, CPU. An avid skydiving enthusiast! Past experience includes Marvell Semiconductors (ThunderX4 architecture team), Cadence Design Systems (Verification IP @ HDMI, I2C, MHL, USB type-C) M.S. thesis in Computer Engineering from NCSU under the guidance of Prof. Eric Rotenberg.U7KARSH.COM
About Me. Currently working at Nvidia as a Sr. Architect, CPU. An avid skydiving enthusiast! Past experience includes Marvell Semiconductors (ThunderX4 architecture team), Cadence Design Systems (Verification IP @ HDMI, I2C, MHL, USB type-C) M.S. thesis in Computer Engineering from NCSU under the guidance of Prof. Eric Rotenberg.U7KARSH.COM
About Me. Currently working at Nvidia as a Sr. Architect, CPU. An avid skydiving enthusiast! Past experience includes Marvell Semiconductors (ThunderX4 architecture team), Cadence Design Systems (Verification IP @ HDMI, I2C, MHL, USB type-C) M.S. thesis in Computer Engineering from NCSU under the guidance of Prof. Eric Rotenberg.U7KARSH.COM
About Me. Currently working at Nvidia as a Sr. Architect, CPU. An avid skydiving enthusiast! Past experience includes Marvell Semiconductors (ThunderX4 architecture team), Cadence Design Systems (Verification IP @ HDMI, I2C, MHL, USB type-C) M.S. thesis in Computer Engineering from NCSU under the guidance of Prof. Eric Rotenberg.U7KARSH.COM
About Me. Currently working at Nvidia as a Sr. Architect, CPU. An avid skydiving enthusiast! Past experience includes Marvell Semiconductors (ThunderX4 architecture team), Cadence Design Systems (Verification IP @ HDMI, I2C, MHL, USB type-C) M.S. thesis in Computer Engineering from NCSU under the guidance of Prof. Eric Rotenberg.U7KARSH.COM
About Me. Currently working at Nvidia as a Sr. Architect, CPU. An avid skydiving enthusiast! Past experience includes Marvell Semiconductors (ThunderX4 architecture team), Cadence Design Systems (Verification IP @ HDMI, I2C, MHL, USB type-C) M.S. thesis in Computer Engineering from NCSU under the guidance of Prof. Eric Rotenberg.U7KARSH.COM
About Me. Currently working at Nvidia as a Sr. Architect, CPU. An avid skydiving enthusiast! Past experience includes Marvell Semiconductors (ThunderX4 architecture team), Cadence Design Systems (Verification IP @ HDMI, I2C, MHL, USB type-C) M.S. thesis in Computer Engineering from NCSU under the guidance of Prof. Eric Rotenberg.U7KARSH.COM
About Me. Currently working at Nvidia as a Sr. Architect, CPU. An avid skydiving enthusiast! Past experience includes Marvell Semiconductors (ThunderX4 architecture team), Cadence Design Systems (Verification IP @ HDMI, I2C, MHL, USB type-C) M.S. thesis in Computer Engineering from NCSU under the guidance of Prof. Eric Rotenberg.Utkarsh Mathur
__
* Personal Details
* Experience
* Publications
* Projects
* Skills
* Awards
Who am I?
PERSONAL DETAILS
* Name: Utkarsh Mathur * Location: San Jose, CA* Email:
u7karsh yahoo co inumathur ncsu edu
* GitHub
* Latest on skydivingABOUT ME
Currently working at Nvidia as a Sr. Architect, CPU. An avid skydivingenthusiast!
Past experience includes Marvell Semiconductors (ThunderX4 architecture team), Cadence Design Systems (Verification IP @ HDMI, I2C, MHL, USB type-C) M.S. thesis in Computer Engineering from NCSU under the guidance of Prof. Eric Rotenberg GPU security under Prof. Huiyang Zhou Research interests: Computer Architecture, General Purpose Computation on Graphics Processors (GPGPU), and architectural support forsecurity.
My Professional BackgroundWORK EXPERIENCE
2021JANUARY - PRESENTNVIDIA
Sr. Architect, CPU
* Working on some core microarch stuff! * More info on this work coming soon ;) 2019AUGUST - 2021JANUARY MARVELL SEMICONDUCTORS Sr. Architecture Engineer * Part of the ThunderX4 server processor architecture team working on on the performance model and RTL * Led the L1D prefetcher project. Was responsible for both performance studies and RTL implementation * Worked on different structures in the load store unit to improveoverall performance
* Worked on different branch prediction schemes and improving fetchbandwidth
* Owned the tracing and simpoints infrastructure for our in-house trace based simulator2018MAY - 2019MAY
NC STATE UNIVERSITY
Research Assistant
Teaching Assistant
* High performance micro-architectural support for load latency hiding in modern superscalar CPUs under Prof. Eric Rotenberg * Architectural support for mitigating timing based side channel attacks on GPUs under Prof. Huiyang Zhou * Teaching Assistant for the courses: * ECE721: Advanced Microarchitecture (Spring '19) * ECE721: Advanced Microarchitecture (Fall '18) 2015OCTOBER - 2017JULY CADENCE DESIGN SYSTEMSR&D Engineer
* Development in Verification IP for the protocols HDMI, MHL & I2c * Co-created a component-based methodology with the aim to have more scalable and flexible architecture of Verification IPs and reducedtime to market
* Created features like Consumer Electronics Control (CEC) Physical Layer, adDDC from scratch Click to browse through more Work Experience 2015JULY - 2015OCTOBER CADENCE DESIGN SYSTEMSR&D Intern
* Learnt various methodologies and trained in tools like ClearCase for Code Version Control * Tested HDMI verification IP and fixed major performance-relatedbugs
2014MAY - 2014AUGUSTADRDE
(DEFENCE R&D ORGANIZATION)Intern
* Developed Data Logger using BL2120 SBC to replace their old firmware and increased recording time by a factor of 10 * Designed schematic layout for data logging systems using dsPIC33F microcontroller for analyzing data recorded by various sensors during free fall to improve parachute designs * Invented a model for non-contact distance measurement of objects using Image Processing to help them determine terminal velocity of freely falling payloads 2014MARCH - 2014APRILROBOVITO
Instructor
* Taught undergraduate level image processing for Robovito. Managed responsibility for lectures, workshops, and project2013JUNE - 2013JULY
NAMPET LABORATORY
IIT KANPUR
Summer Intern
* Developed a software suite in assembly language for the DSP processor TMS320F2812 & incorporated a package of routines to implement any filter of Order 2 * Enabled production of 50Hz three phase sinusoids with various control mechanisms for consistent voltageMy research work?
PATENTS / THESIS / PUBLICATIONS U MATHUR. HW Cain. Effective prefetch throttling based on stream length. US Patent #63/045,681. Filed June 29, 2020. Pending U. MATHUR. Post-Silicon Microarchitecture (PSM) Implementation of Checkpointed Early Load Retirement (CLEAR). M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University,March 2019.
C. Kumar, A. Chaudhary, S. Bhawalkar, U. MATHUR, S. Jain, A. Vastrad, and E. Rotenberg. Post-Silicon Microarchitecture. IEEE Computer Architecture Letters (CAL), 19(1):26-29, Jan.-June 1, 2020. (Date of Publication: 09 March 2020.) Z. Lin, U. MATHUR, and H. Zhou, "Scatter-and-Gather Revisited: High-Performance Side-Channel-Resistant AES on GPUs", The 12th workshop on General-Purpose Computation on Graphics Processing Units(GPGPU-2019), 2019
MATHUR, U., Sharma, R., Srivastava, N., "Script independent angular skew detection and correction algorithms", 2013 International Conference on Signal Processing and Communication (ICSC-2013), IEEE. pp. 466-469, 12-14 Dec. 2013. DOI: 10.1109/ICSPCom.2013.6719835. Sharma, R., MATHUR, U., Srivastava, N., "Angular Skew Correction Algorithm for Handwritten Hindi Text", International Journal of Advance Computer Research; Jun2013, Vol. 3 Issue 2, p43.My latest work
PROJECTS
2018OCTOBER - 2018DEC SIDE CHANNEL RESISTANT IMPLEMENTATION OF AES ON GPUS * Proposed and implemented a high throughput masking based design of AES to mitigate timing based side channel attacks * Studied performance of variants like S-Box, T-Table, Bitsliced, Rivain-Prouff, H-Table, and the proposed for different RNGconfigurations
2018SEPTEMBER - 2018DECOS DESIGN - XINU OS
* Implemented virtual memory abstraction (including virtual stack space) on x86 using 4KB pages * Implemented (1) multi-level feedback queue for process scheduling; (2) spin-lock, guard-lock, try-lock, and priority inheritence GitHub: https://github.com/u7karsh/os_virtual_mem 2018OCTOBER - 2018OCTOBERQUANTUM SECURITY
* Designed and implemented an FPGA synthesizable module for Binary Learning with Errors (LWE), a Quantum Secure Module * Performed power based side channel analysis on the designed module to extract secret information2018MARCH - 2018MAY
LOAD LATENCY HIDING USING LSB (SLICE) AND LVP * Proposed and implemented a micro-arch for continual flow of instructions during retirement stall on L2 miss at head of ROB * Implemented LSB in 721sim (cycle-accurate superscalar simulator) to maintain fake-retired load dependent instructions * Implemented re-insertion of the instructions in slice to issue queue on load value misprediction * Implemented hierarchical store queue with membership test buffer (MTB) to prevent it from becoming a cycle time bottleneck 2018FEBRUARY - 2018MAY MULTIPATH EXECUTION FOR DIVERGENT CONTROL FLOW IN GPUS * The current SIMT stack approach serialize the execution of divergent control flow. We implemented a technique proposed by ElTantawy et. al. (A scalable multi-path microarchitecture for efficient GPU control flow), which allows interleaved execution ofdivergent paths.
* Implemented split table and reconvergence table in GPGPU-sim to allow interleaved execution of divergent paths * Modified scoreboard logic to handle dependencies from divergedpaths correctly
2018FEBRUARY - 2018APRIL PIPELINED LC3 MICROCONTROLLER FUNCTIONAL VERIFICATION * Implemented a layered verification model for LC3 microcontroller in SystemVerilog, including sequencer, driver, monitor, andenvironment
* The package included a coverage plan and several test cases for functional completeness and correctness GitHub: https://github.com/u7karsh/745_lc3_verif 2017NOVEMBER - 2017DECEMBER DYNAMIC INSTRUCTION SCHEDULING * Developed a simulator for an out-of-order superscalar processor based on Tomasulo’s algorithm that fetches, dispatches, and issues N instructions per cycle with integrated two level caches. Perfect branch prediction was assumed GitHub: https://github.com/u7karsh/dynamic_scheduler_ece563 2017OCTOBER - 2017OCTOBER SYNTHESIZABLE CONVOLUTIONAL NEURAL NETWORK * Developed a synthesizable Verilog design for two staged convolutional neural network arithmetic. Design generates 8-bit output vectors for object classification * Two parametrized architectures were proposed and developed with one being throughput and other being area oriented. GitHub: https://github.com/u7karsh/cnn_ece564 2017SEPTEMBER - 2017OCTOBER BRANCH PREDICTOR AND CACHE SIMULATOR * Developed a generic cache simulator for WTWNA, WTWA and WBWA policies which could be used to instantiate any level of memory hierarchy with the option to augment victim cache. Replacement policies like LRU, LFU and LRFU were also incorporated * Worked on a cache simulator for MESI, MOESI and MSI cachecoherence protocols
* Developed a simulator for branch predictor with different configurations like GShare, BiModal, Hybrid with an option to add BTB GitHub: https://github.com/u7karsh/cache_simulator_ece563 https://github.com/u7karsh/branch_predictor_ece563 2015JANUARY - 2015MAY RECONFIGURABLE COMPUTING USING FIELD PROGRAMMABLE GATE ARRAY * Built a computer System on Chip (SoC) on Papilio Pro (Spartan 6) based on Zilog 80 core with 4KB paged Memory Management Unit (64KB virtual, 64MB physical address space) along with 8MB SDRAM with 16KB 4-way associative cache and communication protocol Universal Asynchronous Receiver Transmitter (UART) * Created several programs in assembly to demonstrate features like user input using UART module, arithmetic operations, etc. Click to browse through more Projects2015MARCH - 2015MAY
CRYPTEX
* Created a hardware cryptographic tool using C, Java, Python to securely upload and download files on a cloud * To ensure data security & integrity, system used sessions keys and authentication tokens generated from the hardware using Milenage algorithm that is used in GSM 2015JANUARY - 2015MARCH FPGA PLACE AND ROUTE * Developed open source tool chain using C++ for implementing a place & route mechanism for iCE40 FPGA * Tool chain used already existing FPGA synthesizer (YOSYS) to develop a fully open source FPGA compilation flow 2014AUGUST - 2014DECEMBER HARDWARE SIGNAL PROCESSING TOOLBOX * Designed a low cost (~30$) tool using dsPIC33EP microcontroller for facilitating 3-channel hardware signal processing (up to 1.0MHz bandwidth) that interfaced with MATLAB & JAVA 2014OCTOBER - 2014DECEMBER POSE INVARIANT FACE RECOGNITION * Dataset of 35 males was created manually by taking 5 photographs of each male in different poses * Features were selected using the embedded method for deep learning * Images were cropped & pre-processed using Gabor filter & Histogram Equalization after being converted to gray scale * Keeping all the frontal face images in test set, linear Support Vector Machine achieved an accuracy of 74%2014MAY - 2014JULY
BIFROST
* Centralized & digitized the fee collection data of Jaypee Youth Club through deployment of a central CentOS-based TCP server, that hosted a JAVA-based GUI application for fee collection, receipt printing & uploading data to the server on a channel securely usingPython
* An automated email to every fee depositor as a receipt confirmation was an added feature2013JULY - 2014MAY
MICRO ELECTRO MECHANICAL SYSTEMS (MEMS) * Modelled a Cantilever-based clamped free resonators with Magnetostatic actuation, Piezoresistive detection & Electrostatic actuation, electrostatic detection using Verilog A at the Centre for Microelectromechanical Systems (MEMS) design funded by the National Program on Micro & Smart Systems (NPMASS) initiated by Aeronautical Development Agency (ADA), Govt. of India. 2013AUGUST - 2013SEPTEMBERGRID SOLVING ROBOT
* Robot capable of solving a grid by finding & traversing the shortest path using Dijkstra's algorithm from one node to another without crossing the blocked/restricted nodes * Robot had the capability to pick objects from target nodeautonomously
2013MAY - 2014SEPTEMBERWEBSITES
* Impressions 2013 and 2014: Designed official website of techno-cultural festival at JIIT, Noida * Jaypee Model United Nations 2014: Designed official website forJMUN 2014
* ICSC 2013 and 2015: Designed payment gateway for International Conference on Signal Processing and Communication using JavaServerPages.
Website link: http://u7karsh.com/projects2013APRIL - 2013MAY
FOOT MOUSE
* Developed a system using an accelerometer interfaced with a microcontroller that could easily be attached to a person's shoe * Used this module & C++ interface to control the location of mouse pointer on the Windows platform & performed a left/right clickoperation
* Versatile for games like FIFA & Pro Evolution Soccer 2012JUNE - 2012AUGUST OPENCV-BASED MARKER DETECTION LIBRARY * A robust intensity invariant marker detection framework was developed using OpenCV in C++ to train multiple markers & use it to detect & obtain the Pose Matrices of all markers in a video stream * The Pose Matrix could then be used in a variety of augmentedreality application
What I'm best at
SKILLS & KNOWLEDGE
SOFTWARE
LANGUAGES
C/C++, CUDA, Verilog, SystemVerilog, Python, Assembly for RISC-V, Java, PHP, HTML, SQL, CQLPACKAGES
GPGPU-sim, 721sim (cycle-accurate RISC-V superscalar simulator), MATLAB, ModelSim, Synopsys Design Vision, LaTeXMETHODOLOGIES
UVM ( Universal Verification Methodology )VERSION CONTROL
ClearCase, Perforce, GITOPERATING SYSTEMS
Unix/Linux ❤, WindowsHARDWARE
FPGA
Papilio Pro (Spartan 6)PROCESSORS
TMS320F2812, 8051
CONTROLLERS
dsPIC30 and dsPIC33 family, and ATmega328DEVELOPMENT BOARDS
Arduino, Raspberry Pi and Galileo board What have I acheived?HONOURS AND AWARDS
AISSCE
2009
Merit Certificate holder from CBSE (Science) for being in the top 0.1% of students who appeared in All India Senior School Certificate Examination (AISSCE 2009)HOVERON
January 2014
Secured 1st prize in HoverOn, a line following hovercraft event at Asia's largest Science and Technical Festival, IIT Bombay, 2014 Click here to browse through more AwardsMAGNETO
January 2014
Finalists in Magneto, a gesture controlled robotic event at Asia's largest Science and Technical Festival, IIT Bombay, 2014TRAILBLAZER
March 2013
Awarded 2nd prize in Trailblazer, a manual + autonomous line following bot event, Impressions JIIT, 2013ROBOWARS
September 2012
Received 1st prize in RoboWars, Neuron Malaviya National Institute Technology(MNIT), 2012LINE FOLLOWER
September 2012
Recipient of 2nd prize in Line Follower, Neuron MNIT, 2012RESCUER
September 2012
Awarded 3rd prize in Rescuer, a manual + autonomous grid solving bot event, Neuron MNIT, 2012CONNEXIONS
March 2012
Secured 2nd prize in Connexions, a manual + autonomous line following bot event, Impressions JIIT, 2012 Copyright © 2014-21 Utkarsh Mathur__
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