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OVERVIEW :: HDLC CONTROLLER :: OPENCORES Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. OVERVIEW :: WISHBONE BUS SPECIFICATIONS :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: CF FFT :: OPENCORES Each file is stand-alone and represents a specific configuration. The 2 parameters are: - Number of Points. - Component (Real/Imag) Precision. All designs are pipelined with a synchronous enable and reset. The configuration parameters are coded in the file names: cf_fft_4096_18.v. - 4K point FFT. OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: FLOATING POINT UNIT :: OPENCORESSEE MORE ON OPENCORES.ORG OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Viterbi HDL Code Generator. This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note inWISHBONE B4
Wishbone B4 Chapter 1. Introduction The WISHBONE1 System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a flexible design methodology for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating System-on-Chip integrationproblems.
HOME :: OPENCORESPROJECTSFORUMSABOUTHOWTO/FAQMEDIALICENSING The reference community for Free and Open Source gateware IP cores. Since 1999, OpenCores is the most prominent online community for the development of gateware IP (Intellectual Properties) Cores. It is the place where such cores are shared and promoted in the spirit of Free and Open Source collaboration. The OpenCores portal hosts the source OVERVIEW :: SYNCHRONOUS-DRAM CONTROLLER :: OPENCORES The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specifications. By default the core is configured to work with 512K x 2 Bank x 32-bit SDRAMs such asSamsung
OVERVIEW :: HDLC CONTROLLER :: OPENCORES Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. OVERVIEW :: WISHBONE BUS SPECIFICATIONS :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: CF FFT :: OPENCORES Each file is stand-alone and represents a specific configuration. The 2 parameters are: - Number of Points. - Component (Real/Imag) Precision. All designs are pipelined with a synchronous enable and reset. The configuration parameters are coded in the file names: cf_fft_4096_18.v. - 4K point FFT. OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: FLOATING POINT UNIT :: OPENCORESSEE MORE ON OPENCORES.ORG OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Viterbi HDL Code Generator. This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note inWISHBONE B4
Wishbone B4 Chapter 1. Introduction The WISHBONE1 System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a flexible design methodology for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating System-on-Chip integrationproblems.
OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORES The encoder accepts a parallel 8-bit raw input and generates a parallel 10-bit encoded value based on the data along with a running disparity value. The decoder does the reverse, providing a decoded 8-bit value from the 10-bit encoded input. These cores can be easily incorporated into serializer/deserializer (serdes) communicationsapplications.
OVERVIEW :: HARDWARE ASSISTED IEEE 1588 IP CORE :: OPENCORES Description. Hardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the Precision Time Protocol (IEEE 1588-2008) on 1000M/100M/10M Ethernet networks. PTP packets transmitting and receiving should be implemented by PTP SW protocol stack (PTPd) with existing MAC function; This IP Coreimplements
OVERVIEW :: T80 CPU :: OPENCORES Description. Configurable cpu core that supports Z80, 8080 and gameboy instruction sets. Z80 and 8080 compability have been proven by numerous implementations of old computer and arcade systems. It is used in the zxgate project, a zx81, zx spectrum, trs80 and Jupiter ACE clone project. And also in OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORES Description. Open Source Documented Verilog UART. Purpose. This module was created as a result of my own need for a UART (serial line I/O) component and frustration at the difficulty of integrating the existing available components in to my own project. OVERVIEW :: REED-SOLOMON DECODER/ENCODER :: OPENCORES Description. This core implements Reed-Solomon decoder for the 8-bit wide symbols. The core is designed to occupy fewer amounts of logic blocks, be fast and parametrizable. Main Features: 8-bit input and output data busses. Fully synchronous and pipelined design using OVERVIEW :: DDR3 SDRAM CONTROLLER :: OPENCORES Description. This is a controller core for DDR3 SDRAM. Default configuration supports one 64 bit UDIMM or SO-DIMM. Supports DIMM sizes of 1GB, 2GB, 4GB and 8GB. Works at the minimum DDR3 transfer rate of 600 MT/s. Heavily optimised for Xilinx Spartan 6 FPGA family. OVERVIEW :: MICRO FPGA BOARD :: OPENCORES Description. Micro FPGA board is a stand alone, low cost, do-it-yourself board. All components are possible to get from a local electronics shop (with possible exception of Virtex part). Board includes one Xilinx Virtex XCV100 chip. FPGA is loaded from PC via Xilinx XChecker cable and external power supply must be provided. OVERVIEW :: I2C SLAVE :: OPENCORES Description. i2cSlave is a minimalist I2C slave IP core that provides the basic framework for the implementation of custom I2C slave devices. The core provides a means to read and write up to 256 8-bit registers. These registers can be connected to the users custom logic, thus implementing a simple control and status interface. OVERVIEW :: SGMII :: OPENCORES License: GPL. Generic SGMII / 1000X module that can be connected to any transceiver technology. This core has been verified with 88E1111 Phy. - Autonegotiation. - Rx & Tx in 1000Mbps mode. - Slow bit rate ~ 10Mbps. I don't have adequate tools to verify at full speed. I I2C-MASTER CORE SPECIFICATION OpenCores I2C-Master core 06-03-01 www.opencores.org Rev 0.3 Preliminary 1 of 14 1 Introduction I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of HOME :: OPENCORESPROJECTSFORUMSABOUTHOWTO/FAQMEDIALICENSING The reference community for Free and Open Source gateware IP cores. Since 1999, OpenCores is the most prominent online community for the development of gateware IP (Intellectual Properties) Cores. It is the place where such cores are shared and promoted in the spirit of Free and Open Source collaboration. The OpenCores portal hosts the source OVERVIEW :: SYNCHRONOUS-DRAM CONTROLLER :: OPENCORES The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specifications. By default the core is configured to work with 512K x 2 Bank x 32-bit SDRAMs such asSamsung
OVERVIEW :: HDLC CONTROLLER :: OPENCORES Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Viterbi HDL Code Generator. This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: MICRO FPGA BOARD :: OPENCORES Description. Micro FPGA board is a stand alone, low cost, do-it-yourself board. All components are possible to get from a local electronics shop (with possible exception of Virtex part). Board includes one Xilinx Virtex XCV100 chip. FPGA is loaded from PC via Xilinx XChecker cable and external power supply must be provided. OVERVIEW :: WISHBONE BUS SPECIFICATIONS :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: HARDWARE ASSISTED IEEE 1588 IP CORE :: OPENCORESSEE MOREON OPENCORES.ORG
SPI MASTER CORE SPECIFICATION OpenCores SPI Master Core Specification 3/15/2004 www.opencores.org Rev 0.5 i Revision History Rev. Date Author Description 0.1 June 13, 2002 Simon Srot First DraftWISHBONE B4
Wishbone B4 Chapter 1. Introduction The WISHBONE1 System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a flexible design methodology for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating System-on-Chip integrationproblems.
HOME :: OPENCORESPROJECTSFORUMSABOUTHOWTO/FAQMEDIALICENSING The reference community for Free and Open Source gateware IP cores. Since 1999, OpenCores is the most prominent online community for the development of gateware IP (Intellectual Properties) Cores. It is the place where such cores are shared and promoted in the spirit of Free and Open Source collaboration. The OpenCores portal hosts the source OVERVIEW :: SYNCHRONOUS-DRAM CONTROLLER :: OPENCORES The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specifications. By default the core is configured to work with 512K x 2 Bank x 32-bit SDRAMs such asSamsung
OVERVIEW :: HDLC CONTROLLER :: OPENCORES Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Viterbi HDL Code Generator. This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: MICRO FPGA BOARD :: OPENCORES Description. Micro FPGA board is a stand alone, low cost, do-it-yourself board. All components are possible to get from a local electronics shop (with possible exception of Virtex part). Board includes one Xilinx Virtex XCV100 chip. FPGA is loaded from PC via Xilinx XChecker cable and external power supply must be provided. OVERVIEW :: WISHBONE BUS SPECIFICATIONS :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: HARDWARE ASSISTED IEEE 1588 IP CORE :: OPENCORESSEE MOREON OPENCORES.ORG
SPI MASTER CORE SPECIFICATION OpenCores SPI Master Core Specification 3/15/2004 www.opencores.org Rev 0.5 i Revision History Rev. Date Author Description 0.1 June 13, 2002 Simon Srot First DraftWISHBONE B4
Wishbone B4 Chapter 1. Introduction The WISHBONE1 System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a flexible design methodology for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating System-on-Chip integrationproblems.
OVERVIEW :: MICRO FPGA BOARD :: OPENCORES Description. Micro FPGA board is a stand alone, low cost, do-it-yourself board. All components are possible to get from a local electronics shop (with possible exception of Virtex part). Board includes one Xilinx Virtex XCV100 chip. FPGA is loaded from PC via Xilinx XChecker cable and external power supply must be provided. OPENCORES: EDA TOOLS :: OPENCORES Icarus Verilog Simulator. Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the "vvp" command. OVERVIEW :: APB TO SPI :: OPENCORES Description. APB SPI design is meant to be interfaced with slow-speed peripherals. The initial design will contain APB slave on one side, which will initiate the transactions which can read data from and write data to SPI peripheral. Since SPI is a serial interface, in case of a write, the design will ensure that data obtained through the APB OVERVIEW :: HARDWARE ASSISTED IEEE 1588 IP CORE :: OPENCORES Description. Hardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the Precision Time Protocol (IEEE 1588-2008) on 1000M/100M/10M Ethernet networks. PTP packets transmitting and receiving should be implemented by PTP SW protocol stack (PTPd) with existing MAC function; This IP Coreimplements
OVERVIEW :: FLOATING POINT UNIT :: OPENCORES Description. This is a single precision floating point unit. It is fully IEEE 754 compliant. It can currently perform Add/Sub, Mul and Divide operations, as well as integer to floating point and floating point to integer conversions. It supports four rounding modes: Round to Nearest Even, Round to Zero, Round to +INF and Round to -INF. OVERVIEW :: SHA256 HASH CORE :: OPENCORES The SHA256 hash is a block transformation algorithm based on LFSR message expansion. The algorithm has 2 parts: the Message Schedule and the Hash Core. The message schedule can be implemented as a compact 16-word circular buffer, that is cycled for the 64 clock cycles. Here is a simplified diagram of our implementation of the message schedule OVERVIEW :: VIDEO STREAM SCALER :: OPENCORES Description. The Video Stream Scaler scales streaming video up or down in resolution. Bilinear and nearest neighbor resize. modes are supported. This core provides run-time adjustment of input and output resolution, scaling factors, and scale. type. Compile time OVERVIEW :: SGMII :: OPENCORES License: GPL. Generic SGMII / 1000X module that can be connected to any transceiver technology. This core has been verified with 88E1111 Phy. - Autonegotiation. - Rx & Tx in 1000Mbps mode. - Slow bit rate ~ 10Mbps. I don't have adequate tools to verify at full speed. I OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORES A UART is a useful component for controlling asynchronous (without a separate clock line) serial buses. It can be used via a level converter to talk to the RS232 serial port of a computer. This is not, however, the only application. It can also be used in a circuit to communicate with peripherals, or over other types of cables (such atRS485
OPENCORES
100 rem this program plays 3d tic-tac-toe: 110 dim s(76),r(304),w(20),t(3,14),m(64),l(4) 120 for i=89 to 304: read r(i): next i: 125 for i=1 to 20: read w(i): next i OVERVIEW :: SYNCHRONOUS-DRAM CONTROLLER :: OPENCORES The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specifications. By default the core is configured to work with 512K x 2 Bank x 32-bit SDRAMs such asSamsung
OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Viterbi HDL Code Generator. This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in OVERVIEW :: HDLC CONTROLLER :: OPENCORES Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. OVERVIEW :: CF FFT :: OPENCORES Each file is stand-alone and represents a specific configuration. The 2 parameters are: - Number of Points. - Component (Real/Imag) Precision. All designs are pipelined with a synchronous enable and reset. The configuration parameters are coded in the file names: cf_fft_4096_18.v. - 4K point FFT. OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: ULTIMATE CRC :: OPENCORES Description. Ultimate CRC is a CRC generator/checker. Using generics the core can be fully customized. It creates a function of the data input and the CRC register using XOR-logic. Although the levels of logic gets very high for wide data inputs, the throughput still benefits from this architecture, as can be seen from the synthesispage.
OVERVIEW :: SGMII :: OPENCORES License: GPL. Generic SGMII / 1000X module that can be connected to any transceiver technology. This core has been verified with 88E1111 Phy. - Autonegotiation. - Rx & Tx in 1000Mbps mode. - Slow bit rate ~ 10Mbps. I don't have adequate tools to verify at full speed. I OVERVIEW :: JTAG MASTER :: OPENCORES Description. This is a JTAG Master written in VHDL. It's simulated and tested with XC9500 and the jtag slave from opencores (http://opencores.orgproject,jtag) OVERVIEW :: UART16750 :: OPENCORES Status. - Test script creation done, should cover most functions. - Test log file available. The core was synthesized on a Altera Cyclone II, connected to x86. standard hardware and than tested with standard OS drivers from: - Linux 2.2/2.4/2.6. - Windows 2000/XP/Vista. - *BSD. OVERVIEW :: SYNCHRONOUS-DRAM CONTROLLER :: OPENCORES The Synchronous-DRAM controller core allows any synchronous bus masters, such as most Intel microcontroller and x86 processors, to effortlessly interface to a large capacity SDRAM as though it were an SRAM. The core supports PC100 timing specifications. By default the core is configured to work with 512K x 2 Bank x 32-bit SDRAMs such asSamsung
OVERVIEW :: VITERBI HDL CODE GENERATOR :: OPENCORES Viterbi HDL Code Generator. This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in OVERVIEW :: HDLC CONTROLLER :: OPENCORES Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. OVERVIEW :: CF FFT :: OPENCORES Each file is stand-alone and represents a specific configuration. The 2 parameters are: - Number of Points. - Component (Real/Imag) Precision. All designs are pipelined with a synchronous enable and reset. The configuration parameters are coded in the file names: cf_fft_4096_18.v. - 4K point FFT. OVERVIEW :: 8B10B ENCODER/DECODER :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORESSEE MORE ONOPENCORES.ORG
OVERVIEW :: ULTIMATE CRC :: OPENCORES Description. Ultimate CRC is a CRC generator/checker. Using generics the core can be fully customized. It creates a function of the data input and the CRC register using XOR-logic. Although the levels of logic gets very high for wide data inputs, the throughput still benefits from this architecture, as can be seen from the synthesispage.
OVERVIEW :: SGMII :: OPENCORES License: GPL. Generic SGMII / 1000X module that can be connected to any transceiver technology. This core has been verified with 88E1111 Phy. - Autonegotiation. - Rx & Tx in 1000Mbps mode. - Slow bit rate ~ 10Mbps. I don't have adequate tools to verify at full speed. I OVERVIEW :: JTAG MASTER :: OPENCORES Description. This is a JTAG Master written in VHDL. It's simulated and tested with XC9500 and the jtag slave from opencores (http://opencores.orgproject,jtag) OVERVIEW :: UART16750 :: OPENCORES Status. - Test script creation done, should cover most functions. - Test log file available. The core was synthesized on a Altera Cyclone II, connected to x86. standard hardware and than tested with standard OS drivers from: - Linux 2.2/2.4/2.6. - Windows 2000/XP/Vista. - *BSD. PROJECTS :: OPENCORES Projects :: OpenCores. Written in: Any language VHDL Verilog & VHDL Verilog SystemC Bluespec C/C++ Other. Stage: Any stage Planning Mature Alpha Beta Stable. License: Any license GPL LGPL BSD CERN-OHL-S CERN-OHL-L CERN-OHL2-P Others. Wishbone version: OVERVIEW :: UNSIGNED SERIAL DIVIDER :: OPENCORES The serial_divide_uu is a Verilog coded module that performs binary division. It is fully parameterized, and works in a serial fashion. The number of clock cycles required to complete a divide operation is equal to the number of bits in the quotient plus one. This module has been tested and debugged in actual hardware on a Xilinx XC2S200E FPGA. OVERVIEW :: ULTIMATE CRC :: OPENCORES Description. Ultimate CRC is a CRC generator/checker. Using generics the core can be fully customized. It creates a function of the data input and the CRC register using XOR-logic. Although the levels of logic gets very high for wide data inputs, the throughput still benefits from this architecture, as can be seen from the synthesispage.
OVERVIEW :: DOCUMENTED VERILOG UART :: OPENCORES Description. Open Source Documented Verilog UART. Purpose. This module was created as a result of my own need for a UART (serial line I/O) component and frustration at the difficulty of integrating the existing available components in to my own project. OVERVIEW :: SPI CONTROLLER CORE :: OPENCORES Description. SPI (Serial Peripheral Interface) is serial, synchronous, full duplex communication protocol. It is widely used as a board-level interface between different devices such as microcontrollers, DACs, ADCs and others. This core is SPI/Microwire compliant master serial communication controller with additional functionality. OVERVIEW :: MICRO FPGA BOARD :: OPENCORES Description. Micro FPGA board is a stand alone, low cost, do-it-yourself board. All components are possible to get from a local electronics shop (with possible exception of Virtex part). Board includes one Xilinx Virtex XCV100 chip. FPGA is loaded from PC via Xilinx XChecker cable and external power supply must be provided. OVERVIEW :: REED-SOLOMON DECODER/ENCODER :: OPENCORES Description. This core implements Reed-Solomon decoder for the 8-bit wide symbols. The core is designed to occupy fewer amounts of logic blocks, be fast and parametrizable. Main Features: 8-bit input and output data busses. Fully synchronous and pipelined design using OVERVIEW :: SGMII :: OPENCORES License: GPL. Generic SGMII / 1000X module that can be connected to any transceiver technology. This core has been verified with 88E1111 Phy. - Autonegotiation. - Rx & Tx in 1000Mbps mode. - Slow bit rate ~ 10Mbps. I don't have adequate tools to verify at full speed. IOPENCORES
100 rem this program plays 3d tic-tac-toe: 110 dim s(76),r(304),w(20),t(3,14),m(64),l(4) 120 for i=89 to 304: read r(i): next i: 125 for i=1 to 20: read w(i): next i OVERVIEW :: IPV4 ETHERNET PACKET CREATOR AND TRANSMITTER Description. VHDL implementation of a component that can be connected to the input port of the Virtex-5 Ethernet MAC Local Link Wrapper and that allows for transmission of IPv4 ethernet packets. The complete UDP/IP core that uses this component is the UDP/IP Core project.Username:
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* NEO430 Processor (MSP430-compatible) * miniMIPS Superscalar MOST POPULAR PROJECTS * I2C controller core * SPI Master/Slave Interface * SPI Verilog Master & Slave modules * I2C master/slave Core* I2C Slave
* Ethernet MAC 10/100 Mbps* SPI core
* 10_100_1000 Mbps tri-mode ethernet MAC © copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.Details
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